Struct sunrise_kernel::devices::lapic::LocalVector

#[repr(transparent)]pub struct LocalVector(pub u32);

Allows software to specify the manner in which the local interrupts are delivered to the processor core.

See chapter 10.5.1: Local Vector Table

Implementations

impl LocalVector

fn vector(&self) -> u32

Interrupt vector number.

fn set_vector(&mut self, value: u32)

Interrupt vector number.

fn delivery_mode(&self) -> DeliveryMode

Specifies the type of interrupt to be sent to the processor. Some delivery modes will only operate as intended when used in conjunction with a specific trigger mode. See DeliveryMode for documentation about available modes.

fn set_delivery_mode(&mut self, value: DeliveryMode)

Specifies the type of interrupt to be sent to the processor. Some delivery modes will only operate as intended when used in conjunction with a specific trigger mode. See DeliveryMode for documentation about available modes.

fn delivery_status(&self) -> bool

Indicates the interrupt delivery status, as follows:

• false (Idle): There is currently no activity for this interrupt source, or the previous in-terrupt from this source was delivered to the processor core and accepted.
• true (Send Pending): Indicates that an interrupt from this source has been delivered to the pro-cessor core but has not yet been accepted.

fn polarity(&self) -> bool

Specifies the polarity of the corresponding interrupt pin: (false) active high or (true) active low.

fn set_polarity(&mut self, value: bool)

Specifies the polarity of the corresponding interrupt pin: (false) active high or (true) active low.

fn remote_irr(&self) -> bool

For fixed mode, level-triggered interrupts; this flag is set when the local APIC accepts the interrupt for servicing and is reset when an EOI command is received from the processor. The meaning of this flag is undefined for edge-triggered interrupts and other delivery modes.

fn trigger_mode(&self) -> bool

Selects the trigger mode for the local LINT0 and LINT1 pins: (false) edge sensitive and (true) level sensitive. This flag is only used when the delivery mode is Fixed. When the delivery mode is NMI, SMI, or INIT, the trigger mode is always edge sensitive. When the delivery mode is ExtINT, the trigger mode is always level sensitive. The timer and error interrupts are always treated as edge sensitive.

If the local APIC is not used in conjunction with an I/O APIC and fixed delivery mode is selected; the Pentium 4, Intel Xeon, and P6 family processors will always use level-sensitive triggering, regardless if edge-sensitive triggering is selected.

Software should always set the trigger mode in the LVT LINT1 register to 0 (edge sensitive). Level-sensitive interrupts are not supported for LINT1.

fn set_trigger_mode(&mut self, value: bool)

Selects the trigger mode for the local LINT0 and LINT1 pins: (false) edge sensitive and (true) level sensitive. This flag is only used when the delivery mode is Fixed. When the delivery mode is NMI, SMI, or INIT, the trigger mode is always edge sensitive. When the delivery mode is ExtINT, the trigger mode is always level sensitive. The timer and error interrupts are always treated as edge sensitive.

If the local APIC is not used in conjunction with an I/O APIC and fixed delivery mode is selected; the Pentium 4, Intel Xeon, and P6 family processors will always use level-sensitive triggering, regardless if edge-sensitive triggering is selected.

Software should always set the trigger mode in the LVT LINT1 register to 0 (edge sensitive). Level-sensitive interrupts are not supported for LINT1.

fn masked(&self) -> bool

Interrupt mask: (false) enables reception of the interrupt and (true) inhibits reception of the interrupt. When the local APIC handles a performance-monitoring counters interrupt, it automatically sets the mask flag in the LVT performance counter register. This flag is set to true on reset. It can be cleared only by software.

fn set_masked(&mut self, value: bool)

Interrupt mask: (false) enables reception of the interrupt and (true) inhibits reception of the interrupt. When the local APIC handles a performance-monitoring counters interrupt, it automatically sets the mask flag in the LVT performance counter register. This flag is set to true on reset. It can be cleared only by software.

fn timer_mode(&self) -> TimerMode

Selects timer mode. See TimerMode for possible values.

fn set_timer_mode(&mut self, value: TimerMode)

Selects timer mode. See TimerMode for possible values.

Trait Implementations

impl<T> BitRange<T> for LocalVector where
    u32: BitRange<T>, 

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Clone for LocalVector

fn clone(&self) -> LocalVector

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for LocalVector

impl Debug for LocalVector

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.