Struct sunrise_kernel::devices::ioapic::RedirectionEntry

pub struct RedirectionEntry(pub u64);

Description of a Redirection Entry in the IO-APIC. Unlike IRQ pins of the 8259A, the notion of interrupt priority is completely unrelated to the position of the physical interrupt input signal on the APIC. Instead, software determines the vector (and therefore the priority) for each corresponding interrupt input signal. For each interrupt signal, the operating system can also specify the signal polarity (low active or high active), whether the interrupt is signaled as edges or levels, as well as the destination and delivery mode of the interrupt. The information in the redirection table is used to translate the corresponding interrupt pin information into an inter-APIC message.

The IOAPIC responds to an edge triggered interrupt as long as the interrupt is wider than one CLK cycle. The interrupt input is asynchronous; thus, setup and hold times need to be guaranteed for at lease one rising edge of the CLK input. Once the interrupt is detected, a delivery status bit internal to the IOAPIC is set. A new edge on that Interrupt input pin will not be recongnized until the IOAPIC Unit broadcasts the corresponding message over the APIC bus and the message has been accepted by the destination(s) specified in the destination field. That new edge only results in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt wasn't already pending at the destination.)

Implementations

impl RedirectionEntry

pub fn interrupt_vector(&self) -> u64

The vector field is an 8 bit field containing the interrupt vector for this interrupt. Vector values range from 0x10 to 0xFE.

pub fn set_interrupt_vector(&mut self, value: u64)

The vector field is an 8 bit field containing the interrupt vector for this interrupt. Vector values range from 0x10 to 0xFE.

pub fn delivery_mode(&self) -> DeliveryMode

The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode. These restrictions are indicated in the documentation of [Deliverymode].

pub fn set_delivery_mode(&mut self, value: DeliveryMode)

The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode. These restrictions are indicated in the documentation of [Deliverymode].

pub fn destination_mode(&self) -> bool

This field determines the interpretation of the Destination field. When it is false (physical mode), a destination APIC is identified by its ID. Bits 56 through 59 of the Destination field specify the 4 bit APIC ID.

When this field is true (logicalmode), destinations are identified by matching on the logical destination under the control of the Destination Format Register and Logical Destination Register in each Local APIC.

pub fn set_destination_mode(&mut self, value: bool)

This field determines the interpretation of the Destination field. When it is false (physical mode), a destination APIC is identified by its ID. Bits 56 through 59 of the Destination field specify the 4 bit APIC ID.

When this field is true (logicalmode), destinations are identified by matching on the logical destination under the control of the Destination Format Register and Logical Destination Register in each Local APIC.

pub fn delivery_status(&self) -> bool

The Delivery Status bit contains the current status of the delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bitword) do not effect this bit.

false means IDLE (there is currently no activity for this interrupt).

true means SendPending (the interrupt has been injected but its delivery is temporarily held up due to the APIC bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).

pub fn interrupt_input_pin_polarity(&self) -> bool

This bit specifies the polarity of the interrupt signal. false means High active, true means Low active.

pub fn set_interrupt_input_pin_polarity(&mut self, value: bool)

This bit specifies the polarity of the interrupt signal. false means High active, true means Low active.

pub fn remote_irr(&self) -> bool

This bit is used for level triggered interrupts. Its meaning is undefined for edge triggered interrupts. For level triggered interrupts, this bit is set to true when local APIC(s) accept the level interrupt sent by the IOAPIC. The Remote IRR bit is set to false when an EOI message with a matching interrupt vector is received from a local APIC.

pub fn trigger_mode(&self) -> bool

The trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. true means Level sensitive, false means Edge sensitive.

pub fn set_trigger_mode(&mut self, value: bool)

The trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. true means Level sensitive, false means Edge sensitive.

pub fn interrupt_mask(&self) -> bool

When this bit is 1, the interrupt signal is masked. Edge-sensitive interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the case where the device withdraws the interrupt before that interrupt is posted to the processor. It is software's responsibility to handle the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. When this bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination.

pub fn set_interrupt_mask(&mut self, value: bool)

When this bit is 1, the interrupt signal is masked. Edge-sensitive interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). Level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no side effects. Changing the mask bit from unmasked to masked after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the case where the device withdraws the interrupt before that interrupt is posted to the processor. It is software's responsibility to handle the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. When this bit is 0, the interrupt is not masked. An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination.

pub fn destination_field(&self) -> u64

If the Destination Mode of this entry is Physical Mode, the first 4 bits contain an APIC ID. If Logical Mode is selected, the Destination Field potentially defines a set of processors. The Destination Field specify the logical destination address.

pub fn set_destination_field(&mut self, value: u64)

If the Destination Mode of this entry is Physical Mode, the first 4 bits contain an APIC ID. If Logical Mode is selected, the Destination Field potentially defines a set of processors. The Destination Field specify the logical destination address.

Trait Implementations

impl<T> BitRange<T> for RedirectionEntry where
    u64: BitRange<T>, 

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Debug for RedirectionEntry

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.