Struct sunrise_kernel::devices::hpet::HpetTimerConfigurationRegister

pub struct HpetTimerConfigurationRegister(pub u32);

Represent a Timer Configuration Register.

Implementations

impl HpetTimerConfigurationRegister

pub fn interrupt_type(&self) -> bool

Control Timer Interrupt Type: 0 = Edge Trigger, 1 = Level Trigger

pub fn set_interrupt_type(&mut self, value: bool)

Control Timer Interrupt Type: 0 = Edge Trigger, 1 = Level Trigger

pub fn interrupt_enable(&self) -> bool

Control Timer Interrupt.

pub fn set_interrupt_enable(&mut self, value: bool)

Control Timer Interrupt.

pub fn timer_type(&self) -> bool

Control Timer Type: 0 = One Shot, 1 = Periodic

pub fn set_timer_type(&mut self, value: bool)

Control Timer Type: 0 = One Shot, 1 = Periodic

pub fn periodic_interrupt_capability(&self) -> bool

true if this timer is capable of periodic timer.

pub fn size_capability(&self) -> bool

If this bit is 1, this timer is capable of operating in 64 bit mode.

pub fn accumulator_config(&self) -> bool

Set to 1 to allow software to write the accumulator data.

Note

This auto-clear.

pub fn set_accumulator_config(&mut self, value: bool)

Set to 1 to allow software to write the accumulator data.

Note

This auto-clear.

pub fn is_32bit_mode(&self) -> bool

Set to 1 to force a 64 bit timer to operate as 32 bit one

Note

This as no effect on a 32 bit timer.

pub fn set_32bit_mode(&mut self, value: bool)

Set to 1 to force a 64 bit timer to operate as 32 bit one

Note

This as no effect on a 32 bit timer.

pub fn interrupt_route(&self) -> u32

Timer Interrupt Route: This indicate the routing in the I/O APIC

Note

If the LegacyReplacement Route bit is set, then Timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers.

If the Timer FSB Interrupt bit is set, then the interrupt will be delivered directly to the FSB, and this bit field has no effect.

pub fn set_interrupt_route(&mut self, value: u32)

Timer Interrupt Route: This indicate the routing in the I/O APIC

Note

If the LegacyReplacement Route bit is set, then Timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers.

If the Timer FSB Interrupt bit is set, then the interrupt will be delivered directly to the FSB, and this bit field has no effect.

pub fn fsb_interrupt(&self) -> bool

Timer FSB Interrupt: force the interrupts to be delivered directly as FSB messages, rather than using the I/O APIC.

pub fn set_fsb_interrupt(&mut self, value: bool)

Timer FSB Interrupt: force the interrupts to be delivered directly as FSB messages, rather than using the I/O APIC.

pub fn fsb_interrupt_capability(&self) -> bool

Timer FSB Interrupt Delivery capability.

Trait Implementations

impl<T> BitRange<T> for HpetTimerConfigurationRegister where
    u32: BitRange<T>, 

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Clone for HpetTimerConfigurationRegister

fn clone(&self) -> HpetTimerConfigurationRegister

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for HpetTimerConfigurationRegister

impl Debug for HpetTimerConfigurationRegister

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.