1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
//! AHCI Disk

use alloc::sync::Arc;
use core::fmt::{self, Debug, Formatter};

use spin::Mutex;

use sunrise_libuser::error::{Error, AhciError};
use sunrise_libuser::ahci::IDisk as IDiskInterface;
use sunrise_libuser::futures::WorkQueue;
use sunrise_libuser::zero_box::ZeroBox;
use sunrise_libuser::ahci::Block;

use crate::hba::*;


/// An AHCI Disk
///
/// Manages an AHCI port, and provides functions to read and write sectors.
///
/// # Memory
///
/// A disk is responsible for all allocated memory in use by the port. When dropped, the port
/// is put to a stop, pointers to these regions are cleared from the hardware, and the regions
/// are eventually de-allocated.
///
/// # Lifetime
///
/// A Disk holds a reference to its `Port Control Registers`,
/// which is located in the root `HBA Memory Registers` mapping (the one found at `BAR5`).
///
/// As this root mapping will never be unmapped, the lifetime of this reference is `'static`.
pub struct Disk {

    // memory zones

    /// Pointer back to the corresponding Port Control Registers, found at `BAR5[100h]`-`BAR5[10FFh]`.
    pub(super) px:         &'static mut Px,
    /// The allocated Received FIS memory zone that the port uses.
    pub(super) rfis:       ZeroBox<ReceivedFis>,
    /// The allocated Command List memory zone that the port uses.
    pub(super) cmd_list:   ZeroBox<CmdHeaderArray>,
    /// An allocated Command Table for each implemented Command List slot.
    pub(super) cmd_tables: [Option<ZeroBox<CmdTable>>; 32],

    // info obtained by the IDENTIFY command

    /// Number of addressable sectors of this disk. Each sector is 512 octets.
    pub(super) sectors: u64,
    /// Indicates if the device supports 48 bit addresses.
    pub(super) supports_48_bit: bool,
}

impl Disk {
    /// Returns the number of addressable 512-octet sectors for this disk.
    #[inline(never)]
    fn sector_count(&self, ) -> Result<u64, Error> {
        Ok(self.sectors)
    }

    /// Reads sectors from disk.
    ///
    /// Reads `sector_count` sectors starting from `lba`.
    #[inline(never)]
    fn read_dma(&mut self, buffer: *mut u8, buffer_len: usize, lba: u64, sector_count: u64) -> Result<(), Error> {
        if ((buffer as usize) % 2) != 0 {
            return Err(AhciError::InvalidArg.into());
        }

        if (buffer_len as u64) < sector_count * 512 {
            return Err(AhciError::InvalidArg.into());
        }
        if lba.checked_add(sector_count).filter(|sum| *sum <= self.sectors).is_none() {
            return Err(AhciError::InvalidArg.into());
        }
        // todo: AHCI: Read CI and figure out which slot to use
        // body: For now AHCI driver is single-threaded and blocking,
        // body: which means that the first slot is always available for use.
        // body:
        // body: If we want to make a multi-threaded implementation,
        // body: we will have to implement some logic to choose the slot.
        let command_slot_index = 0;
        let step = if !self.supports_48_bit {
            256
        } else {
            65536
        };

        for sector_step in (0..sector_count).step_by(step) {
            unsafe {
                // safe: - we just mapped buffer, so it is valid memory,
                //         and buffer_len is its length
                //         otherwise mapping it would have failed.
                //       - buffer[0..buffer_len] falls in a single mapping,
                //         we just mapped it.
                //       - command_slot_index is 0, which is always implemented (spec),
                //         and we give the cmd_header and cmd_table of this index.
                //       - px is initialised.
                Px::read_dma(
                    buffer.add(sector_step as usize * 512),
                    buffer_len - sector_step as usize * 512,
                    lba + sector_step,
                    core::cmp::min(sector_count - sector_step, step as u64),
                    self.px,
                    &mut self.cmd_list.slots[command_slot_index],
                    self.cmd_tables[command_slot_index].as_mut().unwrap(),
                    command_slot_index,
                    self.supports_48_bit
                )?
            }
        }
        Ok(())
    }

    /// Writes sectors to disk.
    ///
    /// Writes `sector_count` sectors starting from `lba`.
    #[inline(never)]
    fn write_dma(&mut self, buffer: *const u8, buffer_len: usize, lba: u64, sector_count: u64) -> Result<(), Error> {
        if ((buffer as usize) % 2) != 0 {
            return Err(AhciError::InvalidArg.into());
        }

        if (buffer_len as u64) < sector_count * 512 {
            return Err(AhciError::InvalidArg.into());
        }
        if lba.checked_add(sector_count).filter(|sum| *sum <= self.sectors).is_none() {
            return Err(AhciError::InvalidArg.into());
        }
        let command_slot_index = 0;
        unsafe {
            // safe: - we just mapped buffer, so it is valid memory,
            //         and buffer_len is its length
            //         otherwise mapping it would have failed.
            //       - buffer[0..buffer_len] falls in a single mapping,
            //         we just mapped it.
            //       - command_slot_index is 0, which is always implemented (spec),
            //         and we give the cmd_header and cmd_table of this index.
            //       - px is initialised.
            Px::write_dma(
                buffer,
                buffer_len,
                lba,
                sector_count,
                self.px,
                &mut self.cmd_list.slots[command_slot_index],
                self.cmd_tables[command_slot_index].as_mut().unwrap(),
                command_slot_index,
                self.supports_48_bit
            )?
        }
        Ok(())
    }
}

impl Drop for Disk {
    /// Dropping a disk brings the port to a stop, and clears the pointers from the hardware.
    fn drop(&mut self) {
        self.px.stop();
        self.px.clear_addresses();
    }
}

impl Debug for Disk {
    fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), fmt::Error> {
        f.debug_struct("Disk")
            .field("sectors", &self.sectors)
            .field("px", &self.px)
            .finish()
    }
}

/// Interface to a disk.
#[derive(Debug, Clone)]
pub struct IDisk(Arc<Mutex<Disk>>);

impl IDisk {
    /// Creates an IDisk from the wrapped [Disk].
    pub fn new(value: Arc<Mutex<Disk>>) -> Self {
        Self(value)
    }
}

impl IDiskInterface for IDisk {
    /// Returns the number of addressable 512-octet sectors for this disk.
    fn sector_count(&mut self, _work_queue: WorkQueue<'static>) -> Result<u64, Error> {
        Ok(self.0.lock().sectors)
    }

    /// Reads sectors from disk.
    ///
    /// Reads `sector_count` sectors starting from `lba`.
    ///
    /// # Error
    ///
    /// - InvalidArg:
    ///     - `mapping_size` does not reflect the passed handle's size, or mapping it failed,
    ///     - `lba`, `sector_count`, or `lba + sector_count` is higher than the number of
    ///        addressable sectors on this disk,
    ///     - `sector_count` == 0.
    /// - BufferTooScattered:
    ///     - The passed handle points to memory that is so physically scattered it overflows
    ///       the PRDT. This can only happen for read/writes of 1985 sectors or more.
    ///       You should consider retrying with a smaller `sector_count`.
    fn read_dma(&mut self, _manager: WorkQueue<'static>, address: u64, out_blocks: &mut [sunrise_libuser::ahci::Block]) -> Result<(), Error> {
        self.0.lock().read_dma(out_blocks.as_mut_ptr() as *mut u8, out_blocks.len() * core::mem::size_of::<Block>(), address, out_blocks.len() as u64)
    }

    /// Writes sectors to disk.
    ///
    /// Writes `sector_count` sectors starting from `lba`.
    ///
    /// # Error
    ///
    /// - InvalidArg:
    ///     - `mapping_size` does not reflect the passed handle's size, or mapping it failed,
    ///     - `lba`, `sector_count`, or `lba + sector_count` is higher than the number of
    ///        addressable sectors on this disk,
    ///     - `sector_count` == 0.
    /// - BufferTooScattered:
    ///     - The passed handle points to memory that is so physically scattered it overflows
    ///       the PRDT. This can only happen for read/writes of 1985 sectors or more.
    ///       You should consider retrying with a smaller `sector_count`.
    fn write_dma(&mut self, _manager: WorkQueue<'static>, address: u64, in_blocks: &[sunrise_libuser::ahci::Block]) -> Result<(), Error> {
        self.0.lock().write_dma(in_blocks.as_ptr() as *const u8, in_blocks.len() * core::mem::size_of::<Block>(), address, in_blocks.len() as u64)
    }
}